Many audio applications, such as audio analog to digital converters (ADCs) and audio encoder—decoders (CODECs), utilize a serial data port to transmit digitized audio data to other devices in a system. A typical audio serial data output port outputs bits of a serial audio data (SDOUT) stream in response to an associated serial clock (SCLK) signal. In a stereo system, two channels of audio data are time-multiplexed onto the SDOUT stream with a left-right clock (LRCK) signal. Overall timing is controlled by a master clock (MCLK) signal. At the integrated circuit level, the utilization of a serial port advantageously minimizes the number of pins and associated on-chip driver circuitry.
A typical serial data port operates in either a master mode or a slave mode. In the master mode, the SCLK and LRCK clock signals are generated internally, in response to a received MCLK signal, and output to the destination of the SDOUT stream. In the slave (asynchronous) mode, the SCLK and LRCK clock signals are received from the destination of the SDOUT stream, and therefore may have arbitrary phase relationships with the MCLK signal.
In an ADC, the analog input signal is typically sampled on corresponding rising edges of an internal MCLK clock signal, while data are output on the following edges of the SCLK signal. One frequent problem experienced with ADC serial output ports is the coupling of digital noise into the device substrate from the serial output driver at the SDOUT output, especially when the SDOUT output is driving a relatively high load. For example, if a bit of the SDOUT stream is output on a falling edge of the SCLK clock signal occurring slightly before the next sample of the analog input is taken with the next rising edge of the MCLK signal, digital noise will couple into the ADC analog circuitry through the chip substrate or metal lines.
In the past, the problem of substrate noise generated by the SDOUT output driver has been addressed by re-timing the SCLK clock signal relative to the MCLK clock signal, such that the SDOUT output switching and analog input sampling operations are separated sufficiently in time to prevent digital noise in the substrate from being captured by the analog circuitry. However, in the slave mode, in which the SCLK signal is typically received with an arbitrary phase relationship with the external and/or internal MCLK signals, re-timing is often not possible. In particular, for higher frequency SCLK signals, the timing window between the SCLK signal and the internal MCLK signal may be too small to meet device operating parameters, such as set-up time.
The problem of noise management is compounded when the LRCK signal is taken into account. Depending on the value of the last bit of the current channel and the first bit of the following channel, switching events at the SDOUT pin triggered by LRCK clock signal can cause a noise-generating transition in the state of the SDOUT output driver. For example, if the last bit of the current channel is in a logic low state and the first bit of the following channel is in a logic high state, then on the transition of the LRCK signal, the output driver at the SDOUT pin will transition from sinking to sourcing current, thereby generating noise which can couple through the substrate and/or the device metal lines.
Given the prevalence of serial ports in many data processing applications, and the general goal of minimizing noise within individual devices and the overall system, new noise management techniques suitable for serial port applications are desirable. In particular, these techniques should help minimize noise occurring at transitions of a sampling clock, such as the LRCK signal commonly used in audio applications. Consequently, the noise management task may be focused on addressing noise caused by events triggered the associated serial clock signal.